FPGA implementation of a low power and high speed hybrid multiplier for Image Processing Applications

Valan Arasu, Baul Kani


Multipliers are one of the major dynamic power consuming elements in most of the processor architectures. Hence, there is an essential need to focus on designing multipliers with low dynamic power consumption and if possible with higher operating speed. In this work, considering Very Large Scale Integrated (VLSI) system design, architectural modifications in the conventional hybrid multiplier architecture has been attempted and this helps in minimizing the switching activities, thereby reducing the dynamic power consumption. This also leads to lesser propagation delay. The architectural modification in the conventional hybrid multiplier is made such that a Modified Booth Multiplier (MBM) and Wallace tree multiplier are hybridized with Carry Look-ahead Adder (CLA) to form a low dynamic power consuming high speed hybrid multiplier. In the proposed architecture, MBM is used to reduce the generated partial products whereas Wallace tree multiplier is accompanied for fast addition and the CLA is used for final accumulation.


MBM, Wallace tree multiplier, 3:2 and 4:2 compressors, CLA, Gaussian filter, Mean filter, Wiener filter

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DOI: http://dx.doi.org/10.22385/jctecs.v11i0.162