FPGA implementation of a low power and high speed hybrid multiplier for Image Processing Applications

Valan Arasu, Baul Kani

Abstract


Multipliers are one of the major dynamic power consuming elements in most of the processor architectures. Hence, there is an essential need to focus on designing multipliers with low dynamic power consumption and if possible with higher operating speed. In this work, considering Very Large Scale Integrated (VLSI) system design, architectural modifications in the conventional hybrid multiplier architecture has been attempted and this helps in minimizing the switching activities, thereby reducing the dynamic power consumption. This also leads to lesser propagation delay. The architectural modification in the conventional hybrid multiplier is made such that a Modified Booth Multiplier (MBM) and Wallace tree multiplier are hybridized with Carry Look-ahead Adder (CLA) to form a low dynamic power consuming high speed hybrid multiplier. In the proposed architecture, MBM is used to reduce the generated partial products whereas Wallace tree multiplier is accompanied for fast addition and the CLA is used for final accumulation.


Keywords


MBM, Wallace tree multiplier, 3:2 and 4:2 compressors, CLA, Gaussian filter, Mean filter, Wiener filter

Full Text:

PDF

References


Uvaraj Subramaniam and Srinivasan Alavandar, “Low Power and high Speed computation using Hybridized multiplierâ€, 2013, IEEE-31661, 4th ICCNT-2013.

Jadhav P A Niranjane V B and Kalyani Ingole, “Design of High Speed Hybridized Multiplierâ€, International Journal of Research Studies in Science, Engineering and Technology, June 2015, 2(6).

Naveen Kr. Gahlan, Prabhat Shukla and Jasbir Kaur Implementation of Wallace Tree Multiplier Using Compressor, International Journal of Computer Technology and Applications, 2012, 3 (3): 1194-1199.

Sandeep Shrivastava, Jaikaran Singh and Mukesh Tiwari Implementation of Radix-2 Booth Multiplier and Comparison with Radix-4 Encoder Booth Multiplier, International Journal on Emerging Technologies, 2011, 2(1): 14-16.

Sanjeev Kumar and Manoj Kumar, “Low Power High Speed 3-2 Compressorâ€, International Journal of Electrical, Electronics and Mechanical Controls, May 2013, 2(2).

Satish S Bhairannawar and Rathan R FPGA based efficient Multiplier for Image Processing Applications using Recursive Error Free Mitchell Log Multiplier and KOM Architecture, International Journal of VLSI design & Communication Systems, June 2014, 5(3).

Bodasingi Vijay Bhaskar, Valiveti Ravi Tejesvi and Reddi Surya Prakash Rao, “Implementation of Radix-4 Multiplier with a Parallel MAC unit using MBE Algorithmâ€, International Journal of Advanced Research in Computer Engineering & Technology, Vol. 1, No. 5, July 2012.

Hoang Q. Dao and Vojin G. Oklobdzija Application of Logical Effort on Delay Analysis of 64-Bit Static Carry-Lookahead Adder, 35th Annual Asilomar Conference on Signals, Systems and Computers Pacific Grove, California, 2001.

Wang J S Kuo C N and Yang T H Low-power fixed-width array multiplier, International Symposium on Low Power Electronics Design, 2004, pp: 307–312.

K.N. Vijeyakumar, V. Sumathy ,Sriram Komanduri and C. Chrisjin Gnana Suji, “Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplierâ€, Journal of Computer Science, Vol. 12, No.7,pp:1839-1845,2011.

K. Srishylam, Prof. Syed Amjad Ali, M.Praveena, “Implementation of Hybrid CSA, Modified Booth Algorithm and Transient power Minimization techniques in DSP/Multimedia Applicationsâ€, International Journal of Engineering Research and Applications, Vol. 2, No. 6, 2012, pp.861-871.

P. A. Jadhav, V.B. Niranjane and Kalyani Ingole, “Design of High Speed Hybridized Multiplierâ€, International Journal of Research Studies in Science, Engineering and Technology, Vol. 2, No. 6, June 2015, pp. 110-112.

CH.Rama Koti Reddy, K. Satyavathi, R.Raja Kishore, “A New VLSI Architecture to Increase the speed of computation (Modified Booth Algorithm)â€, International Journal of Research in Computer and Communication Technology, Vol. 2, No. 9, September 2013.

http://bias.csr.unibo.it/fvc2004/download.asp, FVC2004 Database reference, Third Fingerprint verification competition.




DOI: http://dx.doi.org/10.22385/jctecs.v11i0.162