Low Power, Area Efficient Dynamic Voltage Comparator With Reduced Activity Factor

Amol Dnyandev Shinde, Manish Sharma

Abstract


This paper introduces the design of dynamic voltage comparator with reduced activity factor for low voltage and low power operation. An analysis of CMOS circuit power consumption is presented along with implication of activity factor on power consumption. A new architecture based on theoretical analysis for a dynamic comparator is proposed. The proposed comparator has a reduced activity factor and thus it consumes less power and it also has reduced transistor count over the design of double tail dynamic comparator which gives the area efficiency. The proposed design compares small input differential voltages efficiently with low power consumption. All circuit designs are simulated in Tanner tools V16 with 90nm CMOS technology. Simulation result shows that proposed design has less active and standby power consumption.

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DOI: http://dx.doi.org/10.22385/jctecs.v12i0.167