FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard

Muhammad Ibn Ibrahimy

Abstract


This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.

Keywords


Floating-point; Verilog HDL; Carry Look Ahead; Ripple Carry; FPGA

Full Text:

PDF

References


L. Louca, T. A. Cook, W. H. Johnson, “Implementation of IEEE single precision floating point addition and multiplication on FPGAs,†in IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, 1996, pp. 107-116.

G. Renxi, Z. Shangjun, Z. Hainan, M. Xiaobi, G. Wenying, X. Lingling, “Hardware Implementation of a high speed floating point multiplier based on FPGA,†in 4th International Conference on Computer Science & Education, Nanning, China, 2009, pp. 1902–1906.

M. M. ÖZBİLEN, G. A. Mustafa (2009). Single/Double Precision Floating-Point Multiplier Design for Multimedia Applications. Istanbul University - Journal of Electrical & Electronics Engineering. vol. 9. pp. 827–831.

T. L. Floyd, Digital Fundamentals. Upper Saddle River-NJ: Prentice Hall, 2003.

Introduction to DSP – DSP Processors: data formats, Retrieve from

http://www.bores.com/courses/intro/chips/6_data.htm.

IEEE Standard for Floating-Point Arithmetic, IEEE Standard 754-2008, pp. 1-58.

S. Brown, Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, New York : McGraw-Hill Science/Engineering/Math, 2007.

J. M. Lee, Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog. New York: Springer-Verlag, 2002.




DOI: http://dx.doi.org/10.22385/jctecs.v1i0.2